This invention relates to programmable logic array integrated circuits, and more particularly to improved organizations of the logic regions and interconnection conductors of such devices.
Several different "architectures" for programmable logic array devices are known. Pedersen et al. U.S. Pat. No. 5,260,610, for example, shows programmable logic array devices in which blocks of programmable logic regions are disposed on the device in a two-dimensional array of intersecting rows and columns of such blocks. Each block includes a plurality of logic regions and a plurality of local feedback conductors for making the output of any logic region in the block selectively available as an input to any logic region in that block. Global horizontal conductors are associated with each row of blocks for conveying signals between the blocks in that row. Global vertical conductors are associated with each column of blocks for conveying signals from row to row.
The Pedersen et al. architecture has many advantages such as relatively high-speed signal conduction due to the continuous, long, global horizontal and vertical conductors. In some applications, however, this architecture may have certain disadvantages. For example, the blocks are relatively large (e.g., 16 logic regions each), so that relatively large numbers of programmable switches or connectors are required in the local feedback circuitry in each block to make the output of each region available as a possible input to any logic region in the block.
Another possible disadvantage is that any interconnection between blocks uses up at least one global conductor, even though the interconnection may be relatively short (e.g., just to an adjacent block). Also, because the logic region inputs are fed directly from the global horizontal conductors, each global horizontal conductor has many programmably switchable taps along its length. These taps cause significant loading of the global horizontal conductor circuits, which tends to increase the power required to drive those circuits, and which also tends to make those circuits not as fast as they would be with fewer programmable taps.
An architecture which addresses some of the possible disadvantages of the Pedersen et al. architecture is shown in Cliff et al. U.S. Pat. No. 5,260,611. The Cliff et al. architecture reduces the number of switchable taps on the global horizontal conductors by tapping those conductors to block input conductors associated with each block, the number of taps and the number of block input conductors associated with each block being less than the total number of inputs to the logic regions in the block. Each block input conductor is programmably selectively connectable to any logic region in the block, although the number of logic regions in each block is reduced from 16 to eight as compared to the Pedersen et al. architecture.
While the Cliff et al. architecture offers some possible improvements over the Pedersen et al. architecture, it does not improve on the Pedersen et al. architecture in other respects. The Cliff et al. architecture still requires an entire global horizontal or vertical conductor to be used for even relatively short interconnections between blocks. And the Cliff et al. architecture still requires that relatively large programmable connector matrices be provided in each block to make the output of each logic region in the block, as well as each block input conductor, available as an input to any logic region in the block. For example, to make any of eight logic region output signals and any of 24 block input conductors available as inputs to any of the four inputs of each of eight logic regions, a matrix of (8+24).times.4.times.8=1024 programmable connectors is required for each block. In addition to these programmable connectors, other programmable connectors are required to connect the block input conductors to the global horizontal conductors, to apply the logic region outputs to the global horizontal and global vertical conductors, and to interconnect the global horizontal and global vertical conductors. None of these programmable connectors is typically performing any logic, and in all cases many of these connectors are unused.
A very different type of architecture is shown in Freeman U.S. Pat. No. Re. 34,363. In this architecture short interconnection conductors adjacent to each logic region are programmably interconnectable to one another to make interconnections between any but the most closely adjacent logic regions. A possible disadvantage of this architecture is that large numbers of short conductor segments must be "pieced together" to make long interconnections, which tend to be relatively slow due to the large number of programmable switches that the interconnection signal must pass through. More recent commercial products of Freeman's assignee, Xilinx, Inc., have added longer, uninterrupted conductors, and also uninterrupted conductors between adjacent logic regions (see, for example, Carter U.S. Pat. No. 4,642,487). However, these products still rely heavily on piecing together many relatively short interconnection conductor segments to make certain kinds of interconnections.
Another architecture which relies on programmably piecing together axially aligned and adjacent conductors to make longer conductors is shown in El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays," IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, April 1989, pp. 394-98; El-Ayat et al., "A CMOS Electrically Configurable Gate Array," IEEE Journal of Solid-State Circuits, Vol 24, No. 3, June 1989, pp. 752-62; and Elgamal et al. U.S. Pat. No. 4,758,745). This architecture is not reprogrammable. Thus it uses one-time-only programmable connection elements that tend to be smaller and have less circuit loading and signal delay than typical reprogrammable connection elements. With such small one-time-only programmable elements it may be acceptable to provide excess interconnection capacity (e.g., regions of interconnection which are very densely or even fully populated with programmable connection elements) and to rely extensively on piecing together multiple short conductors to make longer conductors. But when a device is to be made reprogrammable, the larger size, loading, and delay of reprogrammable connection elements puts much greater pressure on the device designer to economize as much as possible on the use of such elements, without, of course, unduly sacrificing flexibility in the use of the resulting device. Similar economies are also of interest in connection with one-time-only programmable devices, especially as the logic capacity of those devices increases.
In view of the foregoing, it is an object of this invention to provide improved organizations for the logic regions and interconnection conductors of programmable logic array integrated circuit devices.
It is another object of this invention to provide programmable logic array integrated circuit devices having more effective signal routing, high speed, and greater logic capacity per unit of silicon area.
It is still another object of this invention to reduce the number of programmable switches or connectors that must be provided in programmable logic array devices, to reduce the number of global conductors that must be provided in such devices, and to avoid the piecing together of large numbers of short interconnections conductors that is characteristic of some prior devices.